1. Field of the Invention
The present invention relates to integrated circuits incorporating active devices, such as complementary metal oxide semiconductors (CMOS) and thin-film transistors (TFT), and inductors, and also to a manufacturing method for such integrated circuits. More specifically, the present invention relates to integrated circuits in which induction of eddy current is prevented to thereby improve the performance of inductors and to a manufacturing method for such integrated circuits.
2. Description of the Related Art
Conventional integrated circuits with active devices, such as CMOS, and inductors are fabricated on a standard substrate, which typically consists of a P+ type bulk substrate and an epitaxial layer doped with P type impurities deposited on the bulk substrate.
FIG. 1 shows a cross-section of an integrated circuit of conventional construction. This type of integrated circuits uses a standard substrate that consists of a P+ type bulk substrate 51 and a Pxe2x88x92 type epitaxial layer 52 deposited on the P+ type bulk substrate 51. The P+ type bulk substrate 51 has a resistivity of about 0.01 xcexa9xc2x7cm and is about 700 xcexcm thick. The Pxe2x88x92 type epitaxial layer 52 has a resistivity of about 10 xcexa9xc2x7cm and is about 5 xcexcm thick. A CMOS 55, an active device, is arranged in a region on the surface of the Pxe2x88x92 type epitaxial layer 52. The CMOS 55 includes a P well 53 and an N well 54. An insulating film 56 is disposed on top of the Pxe2x88x92 type epitaxial layer 52 over the region where the CMOS 55 is not arranged, and an insulating film 57 is further disposed over the insulating film 56 and the CMOS 55. An inductor 58 is arranged on a part of the region of the insulating film 57 that corresponds to the insulating film 56. In the integrated circuit as shown in FIG. 1, the use of the standard substrate consisting of the P+ type bulk substrate 51 and the Pxe2x88x92 type epitaxial layer 52 helps prevent occurrences of latch-up events in the CMOS 55 and facilitates impurity gettering in the CMOS 55.
However, the integrated circuit as shown in FIG. 1, in which the P+ type bulk substrate 51 has a low resistivity of about 0.01 xcexa9xc2x7cm, is subjected to eddy-current loss occurring within the P+ type bulk substrate 51 upon operation of the inductor 58. As a result, the Q-value of the inductor 58 is reduced, and so is the performance of the inductor 58.
Although it may be effective to employ a substrate with high resistivity for the sole purpose of suppressing the eddy current, the use of such a highly resistive substrate as the substrate of integrated circuits leads to fluctuation in the substrate voltage and thus to an increased occurrence of latch-up events.
In one technique disclosed in Japanese Patent Laid-Open Publication No. 2000-150783 intended to solve the above-described problems, it is proposed to dispose within the bulk substrate a buried layer heavily doped with impurities. In this manner, the performance of the inductor can be improved without increasing the likelihood of latch-up events.
Nevertheless, the conventional technique is associated with the following problem: in the integrated circuit of the type disclosed in Japanese Patent Laid-Open Publication No. 2000-150783, eddy current is induced and flows through the poorly resistive buried layer, adversely affecting the performance of the inductor.
It is an object of the present invention to provide an improved integrated circuit with an active device, such as CMOS, and an inductor, in which occurrences of latch-up events in the active device have been decreased, have been decreased the generation of eddy current, to improve the performance of the inductor. Also, another object of the present invention is to provide a manufacturing method for manufacturing such integrated circuits.
An integrated circuit according to the present invention comprises an integrated circuit comprising: a semiconductor substrate of a first conductivity type having an active device region and an inductor region that is apart from the active device region; a semiconductor layer of the first conductivity type disposed on the semiconductor substrate, the semiconductor layer having a lower resistivity than the semiconductor substrate; an active device disposed on a surface of the semiconductor layer in the active device region; an insulating film disposed on the semiconductor layer so as to cover the active device; an inductor disposed on the insulating film in the inductor region; and a first layer of the first conductivity type locally disposed between the semiconductor layer and the semiconductor substrate in the active device region, the first layer having a lower resistivity than the semiconductor layer.
One advantage of the present invention is that occurrence of latch-up events is prevented by using a semiconductor substrate with an increased resistivity and disposing a first layer between the semiconductor substrate and the active device. This first layer has a lower resistivity than the semiconductor device. In order to prevent induction of eddy currents, the first layer is not disposed between the inductor and the semiconductor substrate. As a result, the performance of the inductor is improved while the latch-up characteristics of the integrated circuit is ensured. As used herein, the term xe2x80x9cactive devicexe2x80x9d refers to CMOS, TFT, and the like. The resistivity of the semiconductor substrate and the first layer can be controlled for example by adjusting the concentration of impurities to be implanted.
The integrated circuit in accordance with the present invention further comprises a second layer of the first conductivity type locally disposed between the semiconductor layer and the semiconductor substrate in the inductor region, the second layer having a resistivity lower than that of the semiconductor layer but higher than that of the first layer.
The second layer disposed between the inductor and the semiconductor substrate helps ensure some conductivity in the direction parallel to the surface of the semiconductor substrate while preventing induction of eddy currents. As a result, occurrence of latch-up in the active device is prevented and the performance of the inductor is improved. Also, the electrical potential becomes uniform and the current is stabilized in the substrate.
The second layer may be configured as a lattice when viewed from the direction perpendicular to the surface of the semiconductor substrate. Alternatively, the second layer may consist of a plurality of strip-shaped parts that are arranged radially or parallel to one another as viewed from the direction perpendicular to the surface of the semiconductor substrate.
One manufacturing method for an integrated circuit according to the present invention involves locally forming a first layer of a first conductivity type on a semiconductor substrate of the first conductivity type in an active device region of the semiconductor substrate, the first layer having a lower resistivity than the semiconductor substrate; depositing a semiconductor layer of the first conductivity type over the semiconductor substrate and the first layer, the semiconductor layer having a resistivity lower than that of the semiconductor substrate but higher than that of the first layer; disposing an active device on the surface of the semiconductor layer in an active device region; depositing an insulating film over the active device; and disposing an inductor on the insulating film in an inductor region that is apart from the active device region.
Another manufacturing method for an integrated circuit according to the present invention involves forming a second layer of a first conductivity type on a semiconductor substrate of the first conductivity type, the second layer having a lower resistivity than the semiconductor substrate; locally implanting impurities of the first conductivity type into an active device region of the second layer to cause a part of the second layer to become a first layer of the first conductivity type, the first layer having a lower resistivity than the second layer; depositing a semiconductor layer of the first conductivity type over the first layer and the second layer, the semiconductor layer having a resistivity lower than that of the semiconductor substrate but higher than that of the second layer; disposing an active device on the surface of the semiconductor layer in the active device region; depositing an insulating film over the active device; and disposing an inductor on the insulating film in an inductor region of the second layer that is apart from the active device region.
As described in detail, the present invention provides a novel integrated circuit including an active device, such as CMOS and TFT, and an inductor in which occurrence of latch-up events in the active device is prevented, as is induction of eddy currents, so as to improve the performance of the inductor.